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LBR Form 4001-1(a) UNITED STATES BANKRUPTCY COURT SOUTHERN DISTRICT OF OHIO DIVISION In re: Case No: Chapter Debtor(s) Judge RELIEF FROM STAY / ADEQUATE PROTECTION EXHIBIT AND WORKSHEET REAL ESTATE
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laches and flip-flops are the building blocks of computer memory in this particular video will focus on the so-called SR latch later we'll see how this circuit can be enhanced the setreset latch or SR latch for short can be thought of as a 1-bit memory it can be put into one of two stable output States triggered by an input pulse the circuit remembers this state until it's changed again by another input pulse or until the powers removed for this reason the circuit is known as a bi-stable latch before we consider the construction of SR latches let's remind ourselves of some fundamental logic gates this is an or gate and this is the truth table that describes its behavior any combination of inputs a and B results in a 1 an output P except when both inputs are 0 in which case the output is 0 this is an and gate and this is the truth table that describes its behavior any combination of inputs a and B results in a 0 at output P except when both inputs are 1 in which case the output is 1 if we modify the output of a regular or gate by inverting it with a not gate then we can swap the 0 for a 1 and the ones for zeros in the output column of the truth table in a similar fashion we can invert the output of a regular and gate then we can swap the zeros for ones and the one for a zero in the output column of this truth table each of these gate combinations has its own name and its own symbol they are known as the nor gate and that manned gate the nor gate only produces an output of one if both of the inputs are zero the NAND gate only produces an output of zero if both of the inputs are one the SR latch can be built using one of these two basic building blocks let's start by considering an SR latch built from nor gates in this nor gate version of an SR latch two nor gates are connected together in such a way as the output of each nor gate is one of the inputs of the other this cross coupling of two gates results in a form of positive feedback SR latches like all electronic circuits require power to work the power connections aren't shown on this diagram the SR latch has two inputs R and s and the output Q the SR latch also makes the inverse of the output available on this diagram you can see not cube a Q with a bar above it the starting state here is that s and R are both low that is both inputs are 0 Q is high that is the output is warm and not Q the inverse of this is 0 both of the inputs of the top nor gate are 0 so the output of the top gate is 1 this is exactly what you would expect from an or gate the inputs of the lower nor gate are 1 and 0 so the output of the lower gate is 0 because Q is 1 the latch is currently storing 1 now we apply a pulse to input R to reset the latch this changes the output of the top gate and then this is fed back into the lower gate the lower gates output also changes and this is fed back into the top gate the pulse that was applied to reset the SR latch is then removed and re zero again but the output...